The present invention relates to a connection between an electrical component and a substrate. More particularly, the present invention relates to controlling the coefficient of thermal expansion for an underfill between a chip and a substrate (e.g., in flip chip mounting).
Microelectronic devices contain millions of electric circuit components, including transistors assembled in integrated circuit chips, resistors, and capacitors. These electronic components are interconnected to form the circuits, and are eventually connected to and supported on a substrate. The connections are made between electrical terminations on the electronic component and corresponding electrical terminations on the substrate. One method for making these connections includes a flip-chip mounting technique. Flip chips are made by positioning the silicon die (“the chip”) with the active side (“the face”) down on the substrate. Bond pads on the face of the chip are connected by solder bumps or other interconnects to the substrate. During reflow, the solder bumps complete the electrical connections from the active circuitry of the die to the substrate.
During subsequent manufacturing steps, an electronic assembly is subjected to cycles of elevated and lowered temperatures. Because there is a significant difference in the coefficient of thermal expansion (CTE) for the chip, the interconnect material, and the substrate, this thermal cycling can stress the components of the assembly and cause failure at the interconnect points, thereby destroying the functionality of the circuit. To help prevent such failure, the space between the chip and the substrate is underfilled with a dielectric organic material. Once cured, the underfill acts as a buffer between the chip and the substrate and functions to distribute the CTE-induced stress over the entire surface, thereby greatly increasing the life of the finished package. Underfill material also protects the interconnects from moisture and other forms of contamination, and thus, overmolding the back of the chip with epoxy is unnecessary.
The CTE of the underfill material is critical to the reliability of the device because the underfill material compensates for the difference in CTE between the substrate and the chip. In order to reduce solder joint fatigue and extend solder joint life, the CTE of the underfill material should be in the range of about 20 to 40 ppm/° C. at temperatures below its glass transition temperature (Tg).
Underfilling may occur after the reflow of the metallic or polymeric interconnect, or it may occur simultaneously with the reflow. If underfilling occurs after reflow of the interconnect, a predetermined amount of the underfill material may be dispensed at one or more sides of the gap between the chip and the substrate. The material will flow by capillary action into the gap, thereby contacting the solder bumps. Some of the defects that can originate during the flow of fluid underfill include delaminations, where the underfill fails to wet and adhere to a surface, and voids, where contamination causes local variations in the speed of flow and causes bubbles to be trapped. Reducing the viscosity of underfill material, however, enables the material to flow more easily into the small gaps between the silicon die and the substrate. The underfill material is subsequently cured to reach its optimized final properties.
If underfilling occurs simultaneously with reflow of the solder or polymeric interconnects, the underfill material first is applied to either the substrate or the chip. Then terminals on the chip and substrate are aligned and contacted and the assembly is heated to reflow the metallic or polymeric interconnect material. During this heating process, curing of the underfill material occurs simultaneously with reflow of the metallic or polymeric interconnect material.